(1) Field of the Invention
The invention relates to improved power efficiency in microprocessors.
The concept of Hamming distance will first be described. The Hamming distance between two binary numbers is the count of the number of bits that differ between them. For example:
Numbers inNumbers in binaryHammingdecimal(inc. leading zeros)distance4 and 5 0100 and 010117 and 100111 and 101030 and 150000 and 11114
(2) Description of Related Art
Hamming distance is related to power efficiency because of the way that binary numbers are represented by electrical signals. Typically a steady low voltage on a wire represents a binary 0 bit and a steady high voltage represents a binary 1 bit. A number will be represented using these voltage levels on a group of wires, with one wire per bit. Such a group of wires is called a bus. Energy is used when the voltage on a wire is changed. The amount of energy depends on the magnitude of the voltage change and the capacitance of the wire. The capacitance depends to a large extent on the physical dimensions of the wire. So when the number represented by a bus changes, the energy consumed depends on the number of bits that have changed—the Hamming distance—between the old and the new value, and on the capacitance of the wires.
If one can reduce the average Hamming distance between successive values on a high-capacitance bus, keeping all other aspects of the system the same, the system's power efficiency will have been increased.
The capacitance of wires internal to an integrated circuit is small compared to the capacitance of wires fabricated on a printed circuit board due to the larger physical dimensions of the latter.
EP 0,926,596 describes a method of optimizing assembly code of a VLIW processor or other processor that uses multiple-instruction words, each of which comprise instructions to be executed on different functional units of the processor.
EP 0,926,596 describes a method of optimizing assembly code of a VLIW processor or other processor that uses multiple-instruction words, each of which comprise instructions to be executed on different functional units of the processor.